This paper proposes a new high speed low power algorithm for unsigned digital multiplier without pipeline which could be easily expanded to a wider number of bits. The blocks of multiplier works in parallel which significantly increase the speed of multiplier. In proposed algorithm, the input bits of multiplier, are divided into smaller groups of bits which multiplication of these groups are in parallel and simultaneously. This division continues until the minimum number of input bits which is 2×2. In calculating the product of each category, the proposed algorithm is used, which leads to acceleration of the product of each category.The final result will be obtained from the sum of these smaller categories.Modified tree adder have been used to add smaller groups, which can increase the multiplication speed. Multipliers with input bit lengths of 64, 32, 16, 8, 4, and 2 have been implemented using the proposed algorithm in 180 nm and 90 nm technology, which its delay and power consumption with bit length of 32 in 180 nm are 3.05 ns and 40 mW respectively. In 90 nm technology and with the 32 bit length the delay is 1.53 nm and power consumption is 9.7 mW. Also, using the proposed method, it is estimated that the delay of 128×128 bits multiplier in the 180 nm and 90 nm technology are equal to 5.4ns and 2.5ns, respectively. According to the results and in comparison with other works reported in the articles and in the same process, without increasing the power consumption and with a silicon area of 1.5 times, the proposed multiplication speed has increased more than 2 times.
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